Flash memory devices store information as charge in a flash memory cell. Multi-Level (MLC) flash memory devices store k bits per cell using 2 by the power of k levels of charge. The amount of charge depends on the sequence of k bits being stored. For a certain sequence of k bits, the charge being stored may be distributed within a small range. FIG. 1 illustrates a threshold voltage distribution of three bits per cell (bpc) MLC flash memory device, the threshold voltage distribution includes eight lobes 11-18 that represent eight possible logical values, and seven read thresholds 21-27. As long as the lobes are sufficiently distinct, the cell may be reliably read.
The threshold voltage distribution of FIG. 1 illustrates non-overlapping lobes 11-18, however this is only schematic, and in practical cases the lobes may overlap. The overlapping can be intentional—for obtaining high programming speed. Alternatively, the overlapping may result from the retention effect.
A Flash memory device may be partitioned to pages. An old page may introduce greater overlap between lobes than a new page, since after many program and erase (P/E) cycles there is accumulated trap charge, which is de-trapped over time. After a long duration, every lobe may have a larger standard deviation (std) and may have a different mean location. These effects are also known as retention.
Overlap may also occur irrespective of retention. The Flash cells may deteriorate following P/E cycles and the write operation may become less accurate as a result.
The 3-bpc flash memory cell stores a most significant bit (MSB), a central significant bit (CSB) and a least significant bit (LSB). A physical page of Flash memory device may store three logical pages. This physical page is programmed one logical page after the other.
The programming includes various types of programming such as MSB programming, CSB programming and LSB programming.
MSB programming includes programming some of the flash memory cells of a page to a single lobe and some are left in the erase state. At the end of the MSB programming process only two lobes exists, the erase and the MSB lobes.
CSB programming includes splitting the erase lobe and the MSB lobe into two lobes by further programming pulses, depending on the original state of each cell and the corresponding CSB bit. At the end of the CSB programming there are four lobes.
LSB programming includes splitting the four lobes to create 8 lobes.
The logical pages are read by applying various types of read operations such as MSB read (in which a MSB read threshold such as 24 of FIG. 1 is used), CSB read (in which two CSB read thresholds such as read thresholds 22 and 26 of FIG. 1 are used) and LSB read (in which four LSB read thresholds such as read thresholds 21, 23, 25 and 27 of FIG. 1 are used).
FIG. 2 shows similar distributions for the case of 2 bpc devices—four lobes 31-33 and three read thresholds 41-43.
As mentioned, the threshold voltage distributions are not constant throughout the life of the Flash memory device and may change with retention and P/E cycles. With retention, the lobes of the threshold voltage distribution become wider and shift towards the erase level. The higher the retention the larger the shift. This effectively shrinks the effective working window. Both the shrinkage of the window and the fattening of the threshold voltage distributions contribute to the increase in number of errors after performing a page read.
FIG. 3 illustrates these effects—the upper part of FIG. 3 illustrates threshold voltage distribution 60 immediately after programming—it includes spaced apart lobes 61-68 and read thresholds 51-57, while the lower part of FIG. 3 illustrates threshold voltage distribution 80 after retention—it includes partially overlapping lobes 81-88 and read thresholds 71-77. These effects become significantly worse as the block P/E cycles increase and as the NAND Flash memory technology node shrinks.
The retention forces a change in the read thresholds—as using the same set of read thresholds just following a programming operation and following retention may contribute to the number of read errors. It is therefore a need to adjust the read thresholds to reduce read errors.
In order to reduce read errors there is a need to maintain read thresholds per row of flash memory device.
Flash memory devices are typically divided into erase blocks. Each erase block includes multiple rows, where each row includes multiple flash memory cells (cells). All cells in a row are programmed simultaneously. For example, in a 3 bpc MLC device, all MSB bits of all cells in a row are programmed together, all CSB bits are programmed together and all LSB bits are programmed together. Each such group of bits is referred to as a page. All pages in an erase block are erased simultaneously. One cannot erase a single page.
The state of a erase block (which is a function of its retention and endurance) can include the set of optimally positioned read thresholds required to read each of its pages.
For a 3 bpc MLC device which has 64 rows, with 192 pages per block, we would require 64×7=448 read threshold values per block. Note that the state of each row may be defined by the 7 read thresholds illustrated in FIG. 1 (1 for the LSB page, 2 for the CSB page and 4 for the LSB page).
Assuming that each read threshold may require 1 byte of storage and assuming that the entire system may have 10K erase blocks, we would require more than 4 MB to store the state of all the erase blocks in the system. This requirement may be difficult to fulfill in an embedded system.